As is well known, solid state storage devices such as SD cards or solid state drives (SSD) are widely used in various electronic devices.
Generally, a solid state storage device comprises a non-volatile memory. After data are written to the non-volatile memory, if no electric power is supplied to the solid state storage device, the data are still retained in the non-volatile memory.
FIG. 1 is a schematic functional block diagram illustrating a conventional solid state storage device. As shown in FIG. 1, the solid state storage device 10 comprises a control circuit 101 and a non-volatile memory 105. The non-volatile memory 105 further comprises a memory cell array 109. The memory cell array 109 comprises plural memory cells. Generally, the memory cell array 109 is divided into plural blocks, and each block is divided into plural pages.
The solid state storage device 10 is connected with a host 14 through an external bus 12. For example, the external bus 12 is a USB bus, an SATA bus, a PCIe bus, an M.2 bus, a U.2 bus, or the like.
Moreover, the control circuit 101 is connected with the non-volatile memory 105 through an internal bus 113. According to a write command from the host 14, the control circuit 101 stores the write data from the host 14 to the memory cell array 109. Alternatively, according to a read command from the host 14, the control circuit 101 acquires a read data from the memory cell array 109. In addition, the read data is transmitted to the host 14 through the control circuit 101.
Generally, the control circuit 101 stores a default read voltage set. During a read cycle, the control circuit 101 transmits an operation command to the non-volatile memory 105 through the internal bus 113. The control circuit 101 judges the stored data in the memory cell array 109 of the non-volatile memory 105 according to the default read voltage set.
The control circuit 101 further comprises an error correction (ECC) unit 104 for correcting the error bits of the stored data. After the error bits of the stored data are corrected, the read data are correctly read and transmitted to the host 14. However, if the ECC unit 104 is unable to successfully correct all bits of the stored data, the read data is failed to be correctly read and outputted to the host 14. Under this circumstance, the control circuit 101 provides other retry read voltage sets to perform a read retry operation on the non-volatile memory 105.
Depending on the data amount to be stored in the memory cell, the memory cells may be classified into plurality types, i.e. a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC) and a quad-level cell (QLC). The SLC can store only one bit of data per cell. The MLC can store two bits of data per cell. The TLC can store three bits of data per cell. The QLC can store four bits of data per cell. In other words, the memory cell array 109 can be a SLC memory cell array, a MLC memory cell array, a TLC memory cell array or a QLC memory cell array.
In the memory cell array 109, each memory cell comprises a floating gate transistor. By adjusting the number of hot carriers injected into a floating gate of the floating gate transistor, the storing state of the floating gate transistor is adjusted. In other words, the floating gate transistor of each SLC has two storing states, the floating gate transistor of each MLC has four storing states, the floating gate transistor of each TLC has eight storing states, and the floating gate transistor of each QLC has sixteen storing states.
FIG. 2A schematically illustrates the threshold voltage distribution curves of triple-level cells in different storing states. According to the number of injected hot carriers, the triple-level cell has eight storing states “Erase” and “A”˜“G”. Before the hot carriers are injected into the memory cell, the memory cell is in a storing state “Erase”. As the number of the injected hot carriers increases, the memory cell is sequentially in the other seven storing states “A”˜“G”. For example, the memory cell in the storing state “G” has the highest threshold voltage, and the memory cell in the storing state “Erase” has the lowest threshold voltage. After an erase cycle, the memory cell is restored to the storing state “Erase”, and, ideally, no hot carriers are retained in the memory cell.
In practice, even if many memory cells are in the same storing state during the program cycle, the threshold voltages of these memory cells are not all identical. That is, the threshold voltages of these memory cells are distributed in a specified distribution curve with a median threshold voltage. The median threshold voltage of the memory cells in the storing state “Erase” is Ver. The median threshold voltage of the memory cells in the storing state “A” is Va. The median threshold voltage of the memory cells in the storing state “B” is Vb. The median threshold voltage of the memory cells in the storing state “C” is Vc. The median threshold voltage of the memory cells in the storing state “D” is Vd. The median threshold voltage of the memory cells in the storing state “E” is Ve. The median threshold voltage of the memory cells in the storing state “F” is Vf. The median threshold voltage of the memory cells in the storing state “G” is Vg. For example, the median threshold voltage for a greater number of memory cells in the storing state “A” is Va.
Please refer to FIG. 2A again. According to the above characteristics of the triple-level cell, a default read voltage set including seven read voltages Vra˜Vrg is defined. During the read cycle, the control circuit 101 provides the default read voltage set to the non-volatile memory 105 in order to detect the storing states of the triple-level cells of the memory cell array 109.
The storing states of the triple-level cells are determined according to the read voltages Vra˜Vrg. For example, the read voltage Vrg is provided from the control circuit 101 to the memory cell array 109. If the threshold voltage of the memory cell is higher than the read voltage Vrg and the memory cell is turned off, the memory cell is judged to be in the storing state “G”. Whereas, if the threshold voltage of the memory cell is lower than the read voltage Vrg and the memory cell is turned on, the memory cell is not in the storing state “G”. In other words, the eight storing states of the triple-level cells are determined according to the seven read voltages Vra˜Vrg of the default read voltage set.
Similarly, four storing states of the multi-level cells are determined according to three read voltages of the default read voltage set. Similarly, two storing states of the single-level cells are determined according to one read voltage of the default read voltage set.
FIG. 2B schematically illustrates the shift of the threshold voltage distribution curves of triple-level cells in different storing states. In some situations such as a cycling condition, a high/room temperature baking condition or a read disturbing condition, the threshold voltage distribution curves of the memory cells of the memory cell array 109 are possibly shifted. Moreover, if the data retention time of the triple-level cells is very long (e.g., over one month), the threshold voltage distribution curves are possibly shifted.
As shown in FIG. 2B, the threshold voltage distribution curves of the triple-level cells are shifted. The median threshold voltage of the memory cells in the storing state “Erase” is Ver′. The median threshold voltage of the memory cells in the storing state “A” is Va′. The median threshold voltage of the memory cells in the storing state “B” is Vb′. The median threshold voltage of the memory cells in the storing state “C” is Vc′. The median threshold voltage of the memory cells in the storing state “D” is Vd′. The median threshold voltage of the memory cells in the storing state “E” is Ve′. The median threshold voltage of the memory cells in the storing state “F” is Vf′. The median threshold voltage of the memory cells in the storing state “G” is Vg′.
If the storing states of the triple-level cells are determined according to the read voltages Vra˜Vrg of the default read voltage set, the number of error bits in the read data increases. If the ECC unit 104 is unable to successfully correct all bits of the read data, the read data is failed to be correctly read and outputted to the host 14. Under this circumstance, the control circuit 101 provides another retry read voltage set including the read voltages Vra′˜Vrg′ to perform the read retry operation.
FIG. 3 is a flowchart illustrating an error correction method for the conventional solid state storage device. During the read cycle, the control circuit 101 performs a decoding process A. In the decoding process A, a hard decoding operation is performed according to the default read voltage set. That is, the control circuit 101 provides the default read voltage set to the non-volatile memory 105, and the ECC circuit 104 performs the hard decoding operation to correct the read data.
If the error bits in the read data can be corrected, it means that the decoding process A passes and the decoding operation is successfully done. Consequently, the read data is correctly read and transmitted from the control circuit 101 to the host 14. Whereas, if the error bits in the read data cannot be corrected, the read data is not correctly read and the decoding process A fails. Then, the control circuit 101 performs a read retry process.
After the control circuit 101 enters the read retry process, a decoding process B is firstly performed. In the decoding process B, a hard decoding operation is performed according to a retry read voltage set. For example, the control circuit 101 provides the retry read voltage set Vra′˜Vrg′ to the non-volatile memory 105 to acquire the read data. Then, the ECC circuit 104 performs the hard decoding operation to correct the read data. If the error bits in the read data can be corrected, it means that the decoding operation is successfully done to pass the decoding process B. Consequently, the read data is correctly read and transmitted from the control circuit 101 to the host 14. Whereas, if the error bits in the read data cannot be corrected, the read data is not correctly read and the decoding process B fails.
Generally, plural retry read voltage sets (e.g., M retry read voltage sets) have been stored in the control circuit 101. If the decoding operation is successfully done according to one of the plural retry read voltage sets, it means that the decoding process B passes. Whereas, if the data cannot be successfully decoded according to the entire of the M retry read voltage sets, it means that the decoding process B fails. Then, the control circuit 101 performs a decoding process C. Obviously, the time period of performing the decoding process B is longer than the time period of performing the decoding process A.
In the decoding process C, a soft decoding operation is performed according to the retry read voltage set. Generally, the soft decoding operation has better error correction capability than the hard decoding operation. However, while the soft decoding operation is performed, the control circuit 101 acquires one read data according to many retry read voltage sets. In other words, the time period of performing the soft decoding operation is longer. That is, the time period of performing the decoding process C is longer than the time period of performing the decoding process B.
Similarly, if the decoding operation is successfully done by the control circuit 101, it means that the decoding process C passes. Consequently, the read data is correctly read and transmitted from the control circuit 101 to the host 14. Whereas, if the data cannot be successfully decoded by the control circuit 101, it means that the decoding process C fails. Under this circumstance, the control circuit 101 confirms that the read data cannot be correctly read and generates a failed message to the host 14 to indicate that the decoding process fails.
As mentioned above, if the decoding process A fails, the control circuit 101 enters the read retry process. In the read retry process, the control circuit 101 has to perform the decoding process B at first. If the control circuit 101 confirms that the decoding process B fails, the control circuit 101 performs the decoding process C. If the control circuit 101 confirms that the decoding process C fails, the control circuit 101 issues the failed message to the host 14.
If the control circuit 101 cannot acquire the read data in the decoding process A, the control circuit 101 has to enter the read retry process to perform the decoding process B or the decoding process C. However, after the control circuit 101 enters the read retry process, the time period of performing the error correction method of the solid state storage device 10 is very long. Consequently, the read speed of the solid state storage device 10 is largely reduced.